Method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein

ABSTRACT

In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.

This Application is a Divisional of prior Application Ser. No.09/022,733, filed on Feb. 12, 1998, now issued as U.S. Pat. No.5,965,903, to Sailesh Chittipeddi, et al. The above-listed Applicationis commonly assigned with the present invention and is incorporatedherein by reference as if reproduced herein in its entirety under Rule1.53(b).

This is a continuation-in-part of U.S. Ser. No. 08/549,990, filed onOct. 30, 1995, entitled "INTEGRATED CIRCUIT WITH ACTIVE DEVICES UNDERBOND PADS", now U.S. Pat. No. 5,751,065.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed, in general, to integrated circuitsand, more specifically, to integrated circuits having a built in selftest (BIST) circuit and bond pads incorporated therein.

BACKGROUND OF THE INVENTION

The high costs associated with microcircuit manufacture are strongencouragement for determining the acceptability of microdevices at theearliest possible stage of manufacture. Therefore, functional testing atthe semiconductor wafer level is preferred over testing at: (a) themicrocircuit die (a bare, non-incapulated chip) level, or (b) thefinished microdevice level. Conventional chip testing methods todetermine the reliability of semiconductor chips have primarily reliedupon one of the two industry standard procedures: (a) wafer probing, or(b) statistical sampling. Only the first method, wafer probing, appliesat the wafer level; statistical sampling is done at the microcircuit dielevel of production.

At the wafer level, probing technology is generally accomplished at roomtemperature by introducing electrical signals to the necessary circuitsof individual devices to check for appropriate circuit performance. Asemiconductor wafer is approximately eight inches in diameter and maycontain an array of from 50 to 5000 microdevices of the same type.

As wafer probing is typically done at room temperature, performance ofthe microdevice is not evaluated under the thermal load equivalent tofull circuit operation in the microdevice's final form. Thermalscreening at the wafer level is not technically feasible since a thermalforcing technique is not yet available that can rapidly cycle therelatively large mass of a four or five inch semiconductor wafer.Therefore, chip integrity is still questionable after wafer probing.

Next, the devices are cut from the wafer along a preplanned grid, called"streets", and separated into individual microcircuit die. Damageincurred during the wafer cutting process is normally evaluated only byvisual inspection. The die may be tested at this stage of production todetermine the individual reliability of the microchip beforeincorporation into a larger assembly, sometimes known as a HybridMicroelectronic Assembly (HMA). However, exhaustive testing ofindividual die is not economically practical; therefore statisticalsampling of the die batch may be employed.

Statistical sampling is the other industry standard microchip testingprocedure used to determine electrical function and operatingreliability. Using this methodology, one to two percent of theindividual die are separated from the wafer, mounted into a custom testfixture, and subjected to dynamic electrical and thermal evaluation.Based upon the compiled test results, predictions are then madeconcerning the other 98 to 99 percent of chips from that batch. Chips,which were used for testing, are generally not commercially useableafter having been mounted in the fixture and tested.

At the next stage of production electrical wires are attached to thebond pads to provide connectivity between the integrated circuits on thedie and the final electrical circuit. The attachment of wires to thebond pads traditionally introduces certain stresses into themicrocircuit, primarily in the area beneath the bond pads. The die aresubsequently encapsulated into their final electrical package, an HMA.At this level, the final product can again be tested for properfunctionality; however, the entire cost of production has already beenexpended and a failure at this level may result in a total waste of themicrochip.

Therefore, for the most part, chip reliability is uncertain until thechips are assembled in the final electrical package, and the completedHMA package is subjected to final testing. At this point in themanufacturing process, non-functional HMA packages must undergo laborintensive troubleshooting to determine the cause and extent of failure.In many cases the cost of repairing a faulty HMA package exceeds thecost of producing the entire package.

One method of on-wafer functional testing currently in use is that ofbuilt-in test (BIT) or built-in self test (BIST). During these tests, aportion of the semiconductor wafer is designed and manufactured tocreate the signals that test specific critical modules of the individualdevices, when appropriately driven by external test equipment.Unfortunately, however, the BIST circuitry is conventionally placedwithin the principal area of the microchip. The presence of the BISTcircuitry takes away valuable space that could otherwise be used foradditional primary circuitry. Therefore, the capability of testing thecircuit comes at the high price of sacrificing space within themicrochip area, and the useable chip density of the wafer is reduced bythe area dedicated to BIST.

Accordingly what is needed in the art is a device and methodology thatprovides a BIST circuit without reducing the area dedicated to theprimary circuitry.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, thepresent invention provides, in one embodiment, an integrated circuithaving a substrate and active devices formed on the surface of thesubstrate. Other embodiments of the integrated circuit provide forhaving at least either three or four metal layers. In a particularembodiment of the present invention, the integrated circuit comprises abond pad formed over a portion of the active devices. The bond pad has afootprint. As used therein the word footprint means the area covered bythe device to which the word refers. The integrated circuit furtherincludes a patterned metal layer having a metal layer footprint that islocated between the bond pad and the substrate and a built-in self-test(BIST) circuit that has a BIST footprint, which is located between thesubstrate and the bond pad. In this particular embodiment, the bond padfootprint overlays at least a portion of the metal layer footprint andthe BIST footprint. However, in a more advantageous embodiment, the bondpad footprint overlays a substantial portion of the metal layerfootprint and the BIST footprint.

Thus, a broad scope of the present invention provides that a BISTcircuit can be positioned at least partially under the bond pad to makemore efficient use of the space occupied by an electrical circuit, suchas an integrated circuit. This provides distinct advantages over devicesof the prior art in that DIST have been positioned in an area betweenthe bond pad and the integrated circuit, which, of course, reduced theamount of space available for the integrated circuit. However, with thepresent invention, more space is available for the integrated circuit,which is constantly being re-designed to provide more functions forvarious applications.

In an advantageous embodiment, the patterned metal layer is electricallyconnected to the bond pad, and in another embodiment, it is electricallyconnected to at least one device of the active devices.

In another embodiment, the integrated circuit includes a module and theDIST is electrically connected to the module. Of course, it will bereadily apparent to those who are skilled in the art that a plurality ofsuch modules may exist within each integrated circuit. In suchembodiments, the integrated circuit includes a plurality of the moduleslocated on a plurality of die of a semiconductor wafer and furtherincludes a plurality of DIST circuits wherein each of the plurality ofDIST circuits is connected to a different one of the plurality of die.

In yet another embodiment, the integrated circuit further comprises afirst dielectric layer separating the patterned metal layer from thebond pad. In such instances, the patterned metal layer is electricallyisolated from the active devices by a second dielectric layer. Inanother aspect of this particular embodiment, the integrated circuitfurther comprises electrical connections from the bond pad to the activedevice and from the patterned metal layer to the bond pad or the activedevices.

The present invention also provides, in another embodiment, anintegrated circuit wherein the patterned metal layer has a spine with aplurality of areas extending from the spine, and in yet anotherembodiment of the present invention, the patterned metal layer has twoelectrically connected interdigitated combs.

The foregoing has outlined, rather broadly, preferred and alternativefeatures of the present invention so that those skilled in the art maybetter understand the detailed description of the invention thatfollows. Additional features of the invention will be describedhereinafter that form the subject of the claims of the invention. Thoseskilled in the art should appreciate that they can readily use thedisclosed conception and specific embodiment as a basis for designing ormodifying other structures for carrying out the same purposes of thepresent invention. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention in its broadest form.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference isnow made to the following descriptions taken in conjunction with theaccompanying drawings, in which:

FIG. 1 illustrates a top view of an exemplary integrated circuitconstructed according to the principles of the present invention;

FIG. 2 illustrates a sectional view of a portion of the integratedcircuit of FIG. 1 along line 2--2;

FIG. 3 illustrates a sectional view of an alternative embodiment of theintegrated circuit of FIG. 1 along line 2--2;

FIG. 4 illustrates a plan view of one embodiment of the second metallayer of FIG. 2;

FIG. 5 illustrates a plan view of an alternative embodiment of thesecond metal layer of FIG. 2; and

FIG. 6 illustrates a plan view of yet another alternative embodiment ofthe second metal layer of FIG. 2.

DETAILED DESCRIPTION

Contrary to the designs disclosed in conventional devices, one area ofthe microchip that is suitable for inclusion of BIST technology withouta major increase in the size of the chip is the area under the bondpads. The bond pads, which provide the interconnectivity between theintegrated circuits on the die and the electrical circuit in which themicrochip will be installed, are generally located on the periphery ofthe integrated circuit. Bond pads are metal areas, exposed at themicrochip die level, which are electrically connected to the devices inthe integrated circuit via buffers and electrically conductinginterconnects. Conventional bonding technology used to attach wires tothe bond pads require bond pads which have relatively large dimensionswhen compared to microdevice dimensions and therefore occupy asignificant portion of the chip surface. The area underneath the bondpads therefore occupies a substantial fraction of the entire chipsurface.

The electrical connection between the wire and the bond pad requiresphysical integrity as well as high electrical conductivity. Theconventional bonding processes used to form the connection unfortunatelylack the necessary physical integrity to adequately protect thedielectric located under the bond pad from potential damage that canoccur during the bonding process. If the bond pad rests on a dielectric,experience has shown that the bonding conditions often producemechanical stresses in the dielectric. These stresses may cause defectswhich result in leakage currents through the dielectric between the bondpads and the underlying substrate, which is often electricallyconducting. As explained below in detail, the present invention providesan integrated circuit with an improved bond pad structure that allows aBIST to be positioned under the bond pad. This configurationsubstantially reduces the risk of damage to the BIST structure duringthe bonding process and allows more efficient use of chip area.

Referring initially to FIG. 1, illustrated is a top view of an exemplaryintegrated circuit constructed according to the principles of thepresent invention. An integrated circuit chip, generally designated 100,comprises a dielectric layer 101 which overlies the entire chip 100, buthas been patterned to expose portions 105 of a plurality of metal bondpads 103. The primary microcircuitry 110 of the integrated circuit isformed in the center of the chip 100. In the illustrated embodiment, theintegrated circuit chip 100 further comprises a plurality of BISTdevices 120 located underneath and between the bond pads 103.

As one skilled in the art will recognize, combinations of gates, sourceand drain regions, etc., constitute semiconductor circuits which may bedesigned to perform a variety of functions. An integrated circuitcomprises an assemblage of certain combinations of these semiconductordevices which constitute a plurality of electronic modules. Certaintypes of these modules are considered critical to the operation of themicrodevice. These critical modules therefore are those which wouldbenefit most from BIST technology. The critical modules 113 to be testedby the BIST 120 are formed within the primary microcircuitry 110 of theintegrated circuit 100. Individual BIST circuits 120 are electricallyconnected to the appropriate critical modules 113 on a particularmicrochip die by circuit traces 115 formed within the chip 100.

One skilled in the art will recognize that circuitry deposited at anylayer on the surface of a semiconductor wafer creates a distinctfootprint for the given circuitry. Thus, the bond pad 103 and BISTcircuitry 120 create a bond pad footprint and BIST footprint,respectively, which will be shown to affect or protect other circuitryof the chip 100. Of course, it will be appreciated by those who areskilled in the art that there may be a plurality of such bond pads andBISTs as shown in FIG. 1.

Referring now to FIG. 2, illustrated is a sectional view of a portion ofthe integrated circuit of FIG. 1 along line 2--2. A portion of theperiphery of the integrated circuit 100 including the bond pad 103,metal and dielectric layers and active devices under the bond pad 103 isillustrated. Depicted are: a substrate 201, representative activesemiconductor devices 203, a first dielectric layer 205, a seconddielectric layer 207, a first metal layer 211, a third dielectric layer213, a second metal layer 215, a fourth dielectric layer 217, a thirdmetal layer 219, and a fifth dielectric layer 101. The accessibleportion of the third metal layer 219 constitutes the exposed portion 105of the bond pad 103 of FIG. 1. Wire 223 has been bonded to the bond pad103. Dielectric material 217 is formed between metal layers 215 and 219.

For the purposes of further discussion, the BIST circuitry 120 designedto test critical modules 113 within the primary microcircuitry 110 maybe symbolized by representative active devices 203, which is referred toas BIST circuitry 203 below. Windows 251 and 255 in dielectric layers205 and 207 and 217, respectively, provide electrical connectionsbetween substrate 201 and metal layer 211, and metal layers 215 and 219,respectively. In the illustrated embodiment, the second metal layer 215is electrically isolated from the BIST circuitry 203 below by dielectriclayer 213. The metal layer 215 nearest the bond pad 103 provides stressrelief during the bonding process which prevents dielectric layers 205,207, and 213 below the bond pad 103 from cracking. If dielectric layer217 develops defects during bonding, leakage currents do not flow to thesubstrate 201 or BIST circuitry 203. Instead, the leakage currents flowto metal layer 215. The area underneath the bond pads may thus be usedfor BIST circuitry without fear of excessive leakage currents throughthe dielectric layers. With the BIST circuitry located beneath the bondpads, the bond pads may also be spaced more closely together; thisallows more bond pads per linear peripheral distance. Further, a moreefficient use of silicon is achieved with this physical layout, andtherefore a larger yield of die per wafer is realized.

Certain features described generally in the preceding paragraph meritmore comment and detail. The BIST circuitry 203 depicted in FIG. 2 is arepresentative active device, specifically a field effect transistor.The field effect transistor has a gate structure 231, source/drainregions 233 and 235 on opposite sides of gate structure 231, andinsulating sidewalls 237 and 239 on opposite sides of the gate structure231. Gate structure 231 is formed from polysilicon. Insulating portionsof the gate structure 231, such as the gate oxide, are well known tothose skilled in the art. First and second dielectric layers 205 and 207are conformal dielectrics such as TEOS and BPTEOS, respectively. Otherdielectric layers can also be formed from well known deposited oxides ornitrides. The metal layers may be aluminum. Additives, such as silicon,may be present in minor amounts. As shown, a portion of the integratedcircuit, including the BIST circuitry 203, is formed directly under thefootprint of the bond pads 103.

The structure depicted will be readily fabricated by those skilled inthe art using well known techniques to deposit and pattern thedielectric and metal layers and to form the devices. For example, wellknown lithographic, ion implantation, etching, etc., processes may beused. Detailed description of suitable processes is therefore notrequired. The details of an integrated circuit will depend upon theapplications desired for the integrated circuit. The integrated circuitwill be relatively complex, at least by the standards used at thepresent time, to warrant the use of multilevel metal interconnects. Thepackaging connection to the bonding pad is done by any of theconventional and well known techniques presently used.

At least one of the metal layers 211 or 215 is patterned to cover theregion 109 underneath the bond pads 103 and covers at least portions ofthe BIST circuitry 203. In the illustrated embodiment, the second metallayer 215 protects the BIST circuitry 203 during application and bondingof the wire 223. The footprint of the bond pad 103 is substantiallyaligned with the footprint of the second metal layer 215 as well as withthe footprint of the BIST circuitry 203. Metal layer 215 may bepatterned so that it is smaller than metal layer 219, yet extending atleast to the limits of the exposed portion 105 of the bond pad 103. Awindow may then extend from the metal layer 219 directly to the activedevices 203 below the bond pad 103. The window is filled with metalusing well known conventional techniques. This embodiment is desirablebecause it permits the dielectric layers to be thicker than in thepreviously described embodiment. Thicker dielectric layers are lesslikely to crack than are thinner layers.

That the area underneath the bond pads could be used for a BIST locationwas determined by measuring capacitor leakage through a dielectric layerunder various bonding conditions. Although the bonding process stressesthe dielectric layer between the two metal layers, we found that inintegrated circuits with three or more levels of metal that the secondor higher level of metal provided relief from leakage currents in thedielectric.

Variations in the embodiment depicted will be readily thought of bythose skilled in the art. Although an embodiment with three metal layershas been described, more metal layers may be present. Additionally, thebond pads need not be on the periphery of the integrated circuit.Furthermore, the bond pads need not be electrically connected to themetal layer immediately underneath.

Referring now to FIG. 3, illustrated is a sectional view of analternative embodiment of the integrated circuit of FIG. 1 along line2--2. In the embodiment of FIG. 3, note that windows 301 and 303 arepositioned beneath dielectric 101, outside the footprint of the bond padopening 105. By contrast, in FIG. 2, windows 255 are positioned beneaththe footprint of the bond pad opening 105 in dielectric 101. Theembodiment of FIG. 3 prevents damage to the windows 301, 303 duringprobing or wire bonding. The embodiment of FIG. 3 further contains awindow 302 which connects metal layer 215 and metal layer 211. Thuselectrical connectivity is achieved successively from the wire 223through bond pad 219; windows 301, 303; second metal layer 215; window302; first metal layer 211; window 251; and to the BIST circuitry 203located below. One skilled in the art will recognize that thecombination of interconnecting window 302 and placement of windows 301,303 under dielectric 101 are not directly related, but rather isdependent upon the intended integrated circuitry desired.

The metal layer 215 may be formed beneath bond pad 219 in a variety ofpatterns to provide stress relief and to provide necessaryinterconnectivity of the elements of the microdevice. Referring now toFIG. 4, illustrated is a plan view of one embodiment of the second metallayer of FIG. 2. In the illustrated embodiment, the metal layer 215 hasbeen patterned so that a plurality of fingers 413 attach to a spine 410.An extension 405 of spine 410 provides electrical connection to portionsof the circuit which are not under bond pad 219.

Referring now to FIG. 5, illustrated is a plan view of an alternativeembodiment of the second metal layer of FIG. 2. In the embodiment ofFIG. 5, metal layer 215 has openings 507 and provide stress reliefwithin the device. Extension 505 provides electrical connection toportions of the circuit which are not under bond pads 219.

Referring now to FIG. 6, illustrated is a plan view of yet anotheralternative embodiment of the second metal layer of FIG. 2. In theembodiment of FIG. 6, a pair of interdigitated, comb-like structures610, 620 comprise metal layer 215. Structures 610 and 620 areelectrically connected by conductor 630. Extension 605 provideselectrical connection to portions of the circuit which are not underbond pad 219.

Referring now back to FIGS. 1 and 2, those skilled in the art willrecognize from the prior description that the footprint of metal layer215 may be patterned so as to protect the BIST circuitry 120 duringbonding of wires to the bond pads 103. Additionally, it should beapparent that a significant microcircuit density advantage is obtainedover the prior art by placing the BIST circuitry 120 under and betweenthe bond pads 103 versus within the primary microcircuitry 110 of theintegrated circuit 100.

From the foregoing description, it is readily apparent that the presentinvention provides, in one embodiment, an integrated circuit having asubstrate and active devices formed on the surface of the substrate.Other embodiments of the integrated circuit provide for having at leasteither three or four metal layers. In a particular embodiment of thepresent invention, the integrated circuit comprises a bond pad formedover a portion of the active devices. The bond pad has a footprint. Asused therein the word footprint means the area covered by the device towhich the word refers. The integrated circuit further includes apatterned metal layer having a metal layer footprint that is locatedbetween the bond pad and the substrate and a built-in self-test (BIST)circuit that has a BIST footprint, which is located between thesubstrate and the bond pad. In this particular embodiment, the bond padfootprint overlays at least a portion of the metal layer footprint andthe BIST footprint. However, in a more advantageous embodiment, the bondpad footprint overlays a substantial portion of the metal layerfootprint and the BIST footprint.

Although the present invention has been described in detail, thoseskilled in the art should understand that they can make various changes,substitutions and alterations herein without departing from the spiritand scope of the invention in its broadest form.

What is claimed is:
 1. A method of manufacturing an integrated circuithaving a substrate and active devices formed on the surface of saidsubstrate, comprising the steps of:forming a bond pad with a bond padfootprint over a portion of said active devices; forming a patternedmetal layer having a metal layer footprint between said bond pad andsaid substrate; and forming a built-in self-test (BIST) circuit having aBIST footprint between said substrate and said bond pad, said bond padfootprint overlaying at least a portion of said metal layer footprintand said BIST footprint.
 2. The method as recited in claim 1 wherein thestep of forming said patterned metal layer includes the step ofelectrically connecting said patterned metal layer to said bond pad. 3.The method as recited in claim 1 wherein said method further comprisesthe step of forming a plurality of metal levels within said integratedcircuit.
 4. The method as recited in claim 1 further comprising the stepof forming a module and electrically connecting said BIST to saidmodule.
 5. The method as recited in claim 1 wherein said integratedcircuit includes a plurality of circuits located on a plurality of dieof a semiconductor wafer and said method further includes the step offorming a plurality of BIST circuits wherein each of said plurality ofBIST circuits is connected to a different one of said plurality of die.6. The method as recited in claim 1 wherein said step of forming a bondpad includes the step of substantially overlaying said BIST footprintwith said bond pad footprint.
 7. The method as recited in claim 1wherein said step of forming a bond pad includes the step ofsubstantially overlaying said metal layer footprint with said bond badfootprint.
 8. The method as recited in claim 1 further comprising thestep of forming a first dielectric layer separating said patterned metallayer from said bond pad, said patterned metal layer being electricallyisolated from said active devices by a second dielectric layer.
 9. Themethod as recited in claim 1 further comprising the step of formingelectrical connections from said bond pad to said active device and fromsaid patterned metal layer to said bond pad or said active devices. 10.The method as recited in claim 1 wherein said step of forming apatterned metal layer includes the step of forming a spine with aplurality of areas extending from said spine.
 11. The method as recitedin claim 1 wherein said step of forming a patterned metal layer includesthe step of forming two electrically connected interdigitated combs.